In order to read image information from a two-dimensional array of conventional phototransistors, each phototransistor serving as a pixel has an emitter connected to a word line, and a collector connected to a bit line and to a load resistor as illustrated in FIG. 1, and the image information is read from a change of a potential of the collector connected to a load resistor (FIG. 1 is quoted from FIG. 5 in Patent Document 1). A time delay in reading calculated from collector-base capacitance and a load resistance is increased due to the Miller effect, in which a collector potential changes in response to an output signal. A time delay in reading is further caused by stray capacitances between the collector and each of a substrate and an isolation region. A dark current of the phototransistor equivalently increases with a leak current flowing between the collector and each of the substrate and a leak current between the collector and the isolation region being added. A voltage change in the reading operation of a selected phototransistor connected to a bit line is directly applied to a collector of a deselected phototransistor connected to the same bit line, and the deselected phototransistor is disturbed each time another transistor connected to the same bit line is read. For this reason, there has been a limitation to precision detection free from mutual pixel interference and information detection at low illuminance level.
The structure that needs the collector to be isolated from the substrate in this way is hard to make the collector to be sufficiently thick in a direction of the depth of the collector.
Then, it is very difficult to realize high sensitivity down to a wavelength corresponding to near the band gap energy of the semiconductor forming collector by using the semiconductor, such as silicon, having a small light-absorption coefficient in the infrared region.
On the other hand, a one-dimensional linear array technique has been disclosed where each of collectors of an one-dimensional bipolar transistor switch array 48 is connected to turns on and off each of collectors of the phototransistors comprising pixels of an one-dimensional phototransistor array 49 as illustrated in FIG. 2, and a series of photocurrents are read from the emitters of the phototransistors commonly connected within the one-dimensional array (FIG. 5 of Patent Document 1 is quoted, and the reference numerals thereof not necessary in the discussion here are deleted). In this related art example, the collector of the phototransistor is in a floating potential state while being connected to the switch in an off state. If the collector of another phototransistor is connected to the collector, a floating potential interacts with a storage state of optical information of the other phototransistor, causing a disturbance. If the array originally not intended for a two-dimensional array is attempted to be two-dimensional arrayed by merely connecting a plurality of collectors in a two-dimensional arrangement, a two-dimensional array with small mutual interference in pixel information is difficult to realize.
Patent Document 1 also discloses a one-dimensional sensor array technique as illustrated in FIG. 3 (FIG. 6 in Patent Document 1 is quoted, and reference numerals that are not necessary in the discussion herein are omitted), where each collector of a bipolar transistor switch one-dimensional array that turn on and off individual emitter of the phototransistors serving as pixels of a phototransistor one-dimensional array 53 is respectively connected to each emitter of the phototransistors and a photocurrent is read from the collectors of the phototransistors commonly connected within the one-dimensional array. In this related art example, a two-dimensional array version is not originally intended. When the emitter of a phototransistor is connected to the switch that is in an off state, the emitter remains in a floating potential state. If an emitter of another phototransistor is connected to the emitter in an attempt to design a two-dimensional array, the floating potential interacts with a storage state of optical information of the other phototransistor, causing a disturbance. If a plurality of the emitters in the one-dimensional array merely connected, a two-dimensional array with small mutual interference in pixel information is difficult to realize.
Even if a two-dimensional array is designed in accordance with the technique disclosed in Patent Document 1, there is a limitation to precision detection free from mutual pixel interference and to pixel information detection at low illuminance level.
Furthermore, the collectors need to be isolated from a substrate at least on a per row basis or on a per column basis to connect loads to the collectors, or to drive the collectors individually, by row or by column. To this end, this technique needs many different-natured processes including a buried layer diffusion process, an epitaxial growth process, an isolation process, which are different from MOSLSI processes. If a peripheral circuit such as a address selection circuit is implemented using MOSLSI, the technique is not advantageous in terms of quality and number of the manufacturing processes.
An array structure as illustrated in FIG. 4 is disclosed. In the disclosed structure, a pixel is formed by coupling an electric capacitance with a base of an individual transistor, the address selection is performed by a pulse applied to the base via the electric capacitance and an emitter potential change, and the collector of a phototransistor is at a common potential (FIG. 4 is cited from FIG. 1(a) of Non-patent Document 2). However, this technique also causes a disturbance to all deselected pixels having the electric capacitance connected to the one address selection line. There is still a limitation on the detection of an image signal at low illuminance level.
The address selection method by the electric capacitance coupled with the base is also disclosed in FIG. 1, FIG. 2, FIG. 3, FIG. 12, FIG. 17, FIG. 20, FIG. 21, and FIG. 33 of Patent Document 2.
FIG. 5 illustrates a phototransistor one-dimensional array disclosed in FIG. 1 (reference numerals and the like not necessary in the discussion are deleted) of Patent Document 3. Emitters of phototransistors 1a, 1b, . . . , 1f of the one-dimensional array are connected to drains of reading switch FET 2a, 2b, . . . , 2f, and charging switch FET 3a, 3b, . . . , 3f. Sources of the charging switch FETs are connected together to a re-charging voltage VBB. As lines 3 through 5 on the lower portion of the left column on page 2 of the specification reads “the recharging switch is kept to elapse one clock time or longer after a reading operation”, even the linear sensor needs two selection wiring lines for one pixel.
In the related art technique, noise by an address selection pulse to be applied to the gates of FET 2 and FET 3 is superposed to an image signal output terminal 4 via gate-source capacitance of the FETs in the same sign as that of the image signal, and a low-illuminance image signal is hidden in the noise. Patent Document 3 fails to disclose connection for a two-dimensional array, a combination of FETs, the number of wiring lines per pixel, a recharge switch operation phase, etc. If a two-dimensional array is assembled in accordance with the related art technique, the address selection noise gives a limitation on the detection of a low-illuminance level image signal.
FIG. 6 illustrates a phototransistor one-dimensional array having an analog switch for selection of each pixel disclosed in FIG. 1 (reference numerals not necessary in the discussion here are deleted) of Patent Document 4. The analog switch needs to apply to the gate thereof both a pulse transitioning in a positive direction and a pulse transitioning in a negative direction, a pulse noise having the same sign as a read signal is definitely applied via gate-source capacitance in the same sign as an image signal, and a low-illuminance level signal is hidden in the noise. Furthermore, if a potential of a signal output line changes, a potential in the pixel also changes. This not only restricts the operation of a circuit connected to the signal output line, but also causes the noise on the signal output line to enter into the pixel. Also, besides a signal reading line, two wiring lines become necessary on each pixel for cell selection. Since the disclosed phototransistor one-dimensional array does not have a pixel architecture that is intended to be applied into a two-dimensional array, the phototransistor one-dimensional array is not appropriate as a candidate for a pixel architecture for the two-dimensional array.